With improvement in the integration level and operation speed of semiconductor integrated circuit devices, dimensions of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) have been increasingly reduced. Recently, metal gate electrode technology has been actively studied as a solution to presence of a depletion capacitor of a polysilicon gate electrode and boron punch-through to the channel region due to an ultrathin gate electrode film. In particular, FUSI (fully silicided) technology, a technology of forming the entire gate electrode from a metal silicide film, has attracted attention as a promising technology since this technology can be implemented based on the currently used silicon process technology.
In MISFETs using a FUSI gate electrode, an n-MISFET and a p-MISFET are each properly formed and a transistor threshold voltage is controlled by silicide phase control of a FUSI gate electrode. The work function of a metal silicide film changes according to the silicide composition ratio of the metal silicide film. Therefore, by setting the silicide composition ratio of the FUSI gate electrode to a desired value, the work function of the FUSI gate electrode can be adjusted to a desired value and the MIS transistor threshold voltage can be controlled (for example, see Non-patent documents 1 through 4).    Non-patent document 1: J. A. Kittl et. al., “Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths,” VLSI 2005;    Non-patent document 2: A. Lauwers et al., “CMOS Integration of Dual Work Function Phase Controlled Ni FUSI with Simultaneous Silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) Gates on HfSiON,” IEDM 2005;    Non-patent document 3: T. Hoffmann et al., “Ni-based FUSI gates: CMOS Integration for 45 nm node and beyond,” IEDM 2006; and    Non-patent document 4: Y. Tsuchiya et al., “Practical Work Tuning Based on Physical and Chemical Nature of Interfacial Impurity in Ni-FUSI/SiON and HfSiON Systems,” IEDM 2006.
A FUSI gate electrode for an n-MISFET and a FUSI gate electrode for a p-MISFET are each properly formed based on the film thickness ratio of a silicon film for a gate electrode to a nickel film deposited on the silicon film. More specifically, provided that the silicon film thickness is tSi and the nickel film thickness is tNi, the film thickness ratio tNi/tSi needs to be 0.55<tNi/tSi<0.8 in order to form a NiSi-FUSI gate electrode for an n-MISFET. For example, the film thickness ratio needs to be 1.1<tNi/tSi in order to form a Ni2Si-FUSI gate electrode for a p-MISFET. By controlling heat treatment conditions (temperature and time) for causing a reaction between the silicon film and the nickel film so as to satisfy this film thickness ratio, phase control of a FUSI gate electrode for an n-MISFET and a FUSI gate electrode for a p-MISFET is conducted, whereby a FUSI gate electrode for an n-MISFET and a FUSI gate electrode for a p-MISFET are formed.
A MISFET threshold voltage changes according to the work function of the FUSI gate electrode. In the case of a Ni-based FUSI gate electrode, the work function increases as the Ni composition ratio increases. Accordingly, NiSi or NiSi2 is preferable as a FUSI gate electrode for an n-MISFET and Ni2Si, Si31Si12, Ni3Si, or the like is preferable as a FUSI gate electrode for a p-MISFET. These compositions of the FUSI gate electrode are properly used according to a desired threshold voltage. For example, in order to implement a low threshold voltage MISFET, it is preferable to use NiSi2 as a FUSI gate electrode for an n-MISFET and it is preferable to use Ni31Si12 or Ni3Si as a FUSI gate electrode for a p-MISFET.
A conventional manufacturing method of a semiconductor device will now be briefly described with reference to FIGS. 10A through 10D. FIG. 10A is a plan view of the structure of a conventional semiconductor device. FIGS. 10B through 10D are cross-sectional views of a main part of the semiconductor device in the gate width direction taken along line Xd-Xd in FIG. 10A, and sequentially illustrate the steps of a conventional manufacturing method of a semiconductor device. In the figures, the letter “N” on the left-hand side refers to an n-type MIS transistor formation region and the letter “P” on the right-hand side refers to a p-type MIS transistor formation region.
By conducting the same steps as those of a common manufacturing method of a semiconductor device having a polysilicon gate electrode, gate electrode formation films 104a and 104b made of a polysilicon film are formed as shown in FIG. 10B. More specifically, the gate electrode formation film 104a is formed on an active region 100a of an n-type MIS transistor formation region with a gate insulating film 103 interposed therebetween, and the gate electrode formation film 104b is formed on an active region 100b of a p-type MIS transistor formation region with the gate insulating film 103 interposed therebetween. In a p-type well region 102a of a semiconductor substrate 100, the active region 100a is surrounded by an element isolation region 101. In an n-type well region 102b of the semiconductor substrate 100, the active region 100b is surrounded by the element isolation region 101. Thereafter, a sidewall 105 is formed on the side surfaces of the gate electrode formation films 104a and 104b (see FIG. 10A). A resist mask pattern 106 is then formed so as to cover the gate electrode formation film 104a in the n-type MIS transistor formation region. By using the resist mask pattern 106 as a mask, the gate electrode formation film 104b in the p-type MIS transistor formation region is etched so that the gate electrode formation film 104b in the p-type MIS transistor formation region becomes thinner than the gate electrode formation region 104a in the n-type MIS transistor formation region.
As shown in FIG. 10C, the resist mask pattern 106 covering the gate electrode formation film 104a in the n-type MIS transistor formation region is then removed, and a metal film 107 is formed over the whole surface of the semiconductor substrate 100 so as to cover the gate electrode formation films 104a and 104b. For example, the metal film 107 is made of nickel.
In this way, the film thickness ratio of the metal film 107 to the gate electrode formation film 104a in the n-type MIS transistor formation region, that is, the film thickness ratio of nickel to silicon in the n-type MIS transistor formation region, Ni/Si, is made smaller than the film thickness ratio of nickel to silicon in the p-type MIS transistor formation region, Ni/Si.
As shown in FIG. 10D, heat treatment is conducted to cause a reaction between silicon of the gate electrode formation film 104a in the n-type MIS transistor formation region and nickel of the metal film 107 and between silicon of the gate electrode formation film 104b in the p-type MIS transistor formation region and nickel of the metal film 107, whereby metal silicidation of each gate electrode formation region is conducted. The unreacted metal film 107 remaining over the semiconductor substrate 100 is then removed by an etching method.
By thus causing a reaction between the whole gate electrode formation film 104a and the metal film 107 and between the whole gate electrode formation film 104b and the metal film 107, FUSI gate electrodes 108a and 108b are formed in the n-type MIS transistor formation region and the p-type MIS transistor formation region, respectively. The FUSI gate electrode 108a thus obtained is made of a metal silicide film having a silicide composition ratio according to the film thickness ratio of the metal film thickness NNi to the polysilicon film thickness NSi in the FUSI process. Similarly, the FUSI gate electrode 108b is made of a metal silicide film having a silicide composition ratio according to the film thickness ratio of the metal film thickness PNi to the polysilicon film thickness PSi in the FUSI process. FIG. 10D is a cross-sectional view taken along line Xd-Xd in FIG. 10A.
In the conventional manufacturing method of a semiconductor device, the polysilicon film thickness of the gate electrode formation film in the p-type MIS transistor formation region is adjusted by an etching method. In order to accurately implement this adjustment, etching conditions, especially an etching rate and etching time, need to be controlled accurately.
As shown below, however, it is very difficult to accurately control the etching rate, and therefore, the conventional manufacturing method of a semiconductor device has the following problems.
For example, it is very difficult to uniformly adjust the temperature in the chamber (i.e., the etching temperature) between different lots, and therefore the etching rate varies between different lots. Even within the same lot, it is very difficult to uniformly adjust the temperature in the chamber while wafers are sequentially subjected to an etching process. Therefore, the etching rate also varies within the same lot. Accordingly, in the conventional manufacturing method of a semiconductor device, the polysilicon film thickness of the gate electrode formation film in the p-type MIS transistor formation region significantly varies between wafers due to the non-uniform etching rate between different lots and the non-uniform etching rate within the same lot.
Even in the same wafer, a polysilicon film having a large etching area and a polysilicon film having a small etching area are both subjected to the same amount of etching gas regardless of the difference in the etching area. Since the amount of etching gas to the etching area is different, the etching rate is different between these polysilicon films. Therefore, in the conventional manufacturing method of a semiconductor device, the polysilicon film thickness of the gate electrode formation film in the p-type MIS transistor formation region varies even in the same wafer due to the difference in the etching rate.
As described above, the polysilicon film thickness varies between the wafers and even within the same wafer in the conventional manufacturing method of a semiconductor device. Therefore, the polysilicon film thickness varies between the gate electrode formation films in the different p-type MIS transistor formation regions. In other words, the thickness ratio of the metal film to the polysilicon film varies between the gate electrode formation films in the different p-type MIS transistor formation regions.
Even in the gate electrode formation film of the same p-type MIS transistor formation region, the etching rate is different between the end portion and the central portion of the surface of the polysilicon film. Therefore, in the conventional manufacturing method of a semiconductor device, the polysilicon film thickness varies within the gate electrode formation film in the same p-type MIS transistor formation region due to the difference in the etching rate between the end portion and the central portion of the polysilicon film. In other words, such a difference in etching rate between the end portion and the central portion of the polysilicon film causes roughness on the polysilicon film surface. As a result, the film thickness ratio of the metal film to the polysilicon film varies within the gate electrode formation film of the same p-type MIS transistor formation region (in other words, the film thickness ratio is different between the end portion and the central portion of the polysilicon film).
As described above, in the conventional manufacturing method of a semiconductor device, the film thickness ratio varies between the gate electrode formation films in the different p-type MIS transistor formation regions and also varies within the gate electrode formation film in the same p-type MIS transistor formation region. As a result, the silicide composition ratio of the metal silicide film varies between the different p-type MIS transistors and also varies within the same p-type MIS transistor (in other words, the silicide ratio is different between the end portion and the central portion of the metal silicide film).
Accordingly, in the conventional manufacturing method of a semiconductor device, a FUSI gate electrode made of a metal silicide film having a desired silicide composition ratio can be obtained in an n-type MIS transistor. However, a FUSI gate electrode made of a metal silicide film having a desired silicide composition ratio cannot be obtained in a p-type MIS transistor, that is, in a MIS transistor having its polysilicon film thickness adjusted by etching. In other words, it is impossible to obtain a FUSI gate electrode made of a metal silicide film having a desired silicide composition ratio in both an n-type MIS transistor and a p-type MIS transistor.
Therefore, in the conventional manufacturing method of a semiconductor device, the threshold voltage of an n-type MIS transistor can be controlled to a desired value, while the threshold voltage of a p-type MIS transistor cannot be controlled to a desired value. It is therefore impossible to obtain a desired threshold voltage in both an n-type MIS transistor and a p-type MIS transistor.
As shown in FIG. 10B, the polysilicon film has a stepped portion at the boundary between the gate electrode formation film 104a in the n-type MIS transistor formation region and the gate electrode formation region 104b in the p-type MIS transistor formation region. In the step of FIG. 10C, heat treatment is conducted to cause a reaction between silicon of the gate electrode formation film 104a in the n-type MIS transistor formation region and the gate electrode formation film 104b in the p-type MIS transistor formation region and nickel of the metal film 107. Since the polysilicon film has a stepped portion at the boundary, nickel is supplied not only from the top surface but the exposed part of the side surface of the gate electrode formation film 104a in the n-type MIS transistor formation region during the metal silicidation process. Therefore, nickel is oversupplied in a region adjacent to the p-type MIS transistor formation region in the gate electrode formation film 104a in the n-type MIS transistor formation region. As a result, the silicide composition is likely to vary in this region and a silicide composition mixed region 108c is likely to expand as shown in FIG. 10D. When the silicide composition mixed region 108c expands over the active region 100a in the n-type MIS transistor formation region or the active region 100b in the p-type MIS transistor formation region, the transistor threshold voltage varies, and a desired threshold voltage cannot be obtained. In order to avoid the above problems, a larger element isolation region 101 may be formed to separate the active region 100a in the n-type MIS transistor formation region and the active region 100b in the p-type MIS transistor formation region. However, this hinders dimensional reduction of a semiconductor integrated circuit device.